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| TC9WMB1AFK/FU,TC9WMB2AFK/FU TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic TC9WMB1AFK,TC9WMB1AFU,TC9WMB2AFK,TC9WMB2AFU TC9WMB1AFK/FU: 1024 Bit (128 x 8 Bit) 2 Wire Serial EEPROM TC9WMB2AFK/FU: 2048 Bit (256 x 8 Bit) 2 Wire Serial EEPROM The TC9WMB1A and TC9WMB2A are electrically erasable/programmable nonvolatile memory (EEPROM). TC9WMB1AFK,TC9WMB2AFK Features * * 2-wire serial interface (I2C BUS) Single power supply Read: VCC = 1.8 to 3.6 V Write: VCC = 2.3 to 3.6 V Low power consumption: 5 A (in standby state) 0.5 mA (in read state) Operating frequency: 400 kHz (VCC = 2.3 to 3.6 V) Byte write and page (8-byte) write Write protection Sequential read Write time: 10 ms (VCC = 3.0 to 3.6 V) 12 ms (VCC = 2.3 to 2.7 V) Rewrite endurance: 105 times Data retention: 10 years Wide operating temperature range: -40 to 85C Package: US8, SM8 SM8 US8 TC9WMB1AFU,TC9WMB2AFU * * * * * * * * * * Weight: SSOP8-P-0.50A: 0.01 g (typ.) SSOP8-P-0.65: 0.02 g (typ.) Product Marking Pin Assignment (top view) VCC WP SCL SDA 5 8 7 6 US8 Part number 9WM B 1A, 2A Pin 1 index 1 SM8 Part number A0 2 A1 3 4 A2 GND WMB 1A, 2A LotNo. Pin 1 index 1 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU Block Diagram Address inputs A0 A1 A2 Serial clock input SCL Serial input/output SDA Timing generator Control circuit Power supply (booster circuit) VCC Power supply Write protection input WP Command register Memory cell Input/Output circuit Address Address register decoder GND Ground Data register Pin Function Pin Name SCL Input/Output Input Description Serial clock input Data is latched on the rising edge of SCL and transferred the falling edge of SCL. Serial input/output This pin must be pulled up with a resistor because it is configured as an N-ch open-drain pin for output. Write protection input A high on this input disables writing. A low on this input enables writing. Address input This pin is used to configure the slave address. 1.8 to 3.6 V (for reading) 2.3 to 3.6 V (for writing) 0 V (GND) SDA Input/output WP A0, A1, A2 VCC GND Input Input Power supply 2 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU Functional Description 1. Start and Stop Conditions When SCL is high, pulling SDA low produces a start condition and pulling SDA high produces a stop condition. Every instruction is started when a start condition occurs and terminated when a stop condition occurs. During a read, a stop condition causes the read to terminate and the device to enter the standby state. During a write, a stop condition causes the fetching of write data to terminate, after which writing starts automatically. Upon the completion of writing, the device enters the standby state. Start conditions of five times or more cannot be generated from stop condition to the next stop condition. tSU.STA tHD.STA SCL tSU.STO SDA Start condition Stop condition Figure 1 2. Modifying Data Data on the SDA input can be modified while SCL is low. When SCL is high, modifying the SDA input means a start or stop condition. tSU.DAT SCL tHD.DAT SDA Modify data Modify data Figure 2 3 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU 3. Acknowledge Data is transmitted in 8-bit units. The device sends "low" of an acknowledge signal, by pulling SDA during the 9th clock cycle, indicating that it has received data normally. The host releases the bus in the 9th clock cycle to receive an acknowledge signal. During a write operations, the device is always the receiver so that an acknowledge signal is sent each time it has received 8-bit of data. During a read operations, the device sends an acknowledge signal after it receives an address following a start condition. Then, a read data is sent and releases the bus to wait for an acknowledge signal from the master. When an acknowledge signal is detected, next address data is sent if a stop condition is not detected. If the device does not detect an acknowledge signal, a read operations is stopped, and enters the standby mode when a stop condition occurs subsequently. If the device does not detect an acknowledge signal nor a stop condition, it keeps the bus released. SCL 1 8 9 SDA (input) SDA (output) tAA Start condition Acknowledge output tDH Figure 3 4. Device Addressing After a start condition occurs, 7-bit device address and a 1-bit read/write instruction code are transferred to the device. The first four bits are called device code, which must always be "1", "0", "1", "0". The next two bits are called slave address and are used to select a device on the bus. The slave address is compared to the value on the address inputs (A0, A1 and A2). The least significant bit ( R/ W : READ/ WRITE ) indicates a read instruction when set to "1" and a write instruction when set to "0". An instruction is not executed if the device address does not match the specified value. Read/write instruction code Device address Device code 1 0 1 0 Slave address A2 A1 A0 R/W LSB MSD Figure 4 4 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU 5. Write Operation (1) Byte write A data is written to the specified address at a byte write operation. After a start condition, a device address, R/ W (= 0), a word address, and write data are received to the device. When a stop condition is generated subsequently, write operation starts automatically, rewriting the data at the specified address with the input data. A next instruction cannot be received while write operation is in progress. Therefore, no acknowledge signal is returned. After writing the data, the device automatically enters the standby state. S T A R T SDA LINE W R I T E S T O P DEVICE ADDRESS 1010 M S B WORD * ADDRESS WWWWWWWW 76543210 LA SC BK WRITE DATA DDDDDDDD 76543210 A C K AAA 0 210 L RAM S / CS BW K B *: Optional for the TC9WMB1A. Address increment Figure 5 (2) Page write A Data is written up to 8 bytes to the specified page at a page write operation. After a start condition, a device address, R/ W (= 0), a word address (n), and write data (n) are received to the device, in the same way as for a byte write operation. Then, write data (n + 1) is immediately received without entering a stop condition, while checking that an acknowledge signal is asserted (0). The first five bits (W3 to W7) of the word address are the same and the lower three bits (W0 to W2) are automatically incremented so that up to 8 bytes of data can be written. When the last address within the page is reached, the lower three bits (W0 to W2) of the word address are rolled over to the first address of the page. If more than 8 bytes of write data are transferred, the last 8 bytes are valid. When a stop condition is generated subsequently, write operation starts automatically, rewriting the data at the specified addresses with the input data. S T A R T SDA LINE W R I T E S T O P DEVICE ADDRESS 1010 M S B * WORD ADDRESS (n) WRITE DATA (n) DDDDDDDD 76543210 A C K Address increment WRITE DATA (n + 1) DDDDDDDD 76543210 A C K Address increment WRITE DATA (n + m) DDDDDD 543210 A C K AAA 0 210 LRA S/C BW K WWWWWWWW 76543210 *: Optional for the TC9WMB1A. Address increment Figure 6 5 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU (3) Acknowledge polling Acknowledge polling is a feature for determining whether rewrite operation is in progress. During rewrite operation, generate a start condition followed by a device address, and R/ W (= 0 or 1). The acknowledge feature does not generate an acknowledge signal while rewrite operation is in progress. A low acknowledge signal is generated if rewriting has already completed. If the next instruction is a write, supply a word address and write data subsequently. If the next instruction is a read, supply a stop condition and then start read operation. Write protection When "high" is received to the write protection (WP) pin, the TC9WMB1A to protect the entire memory area from being written and the TC9WMB2A to protect the bottom half (80h to FFh) of the memory area from being written. Rewriting is allowed when "low" is received to the write protection pin. While a write is in progress, driving the WP pin high does not stop write operation. Reading is always enabled regardless of whether the WP pin is "high" or "low" (4) 6. Read Operation Read operation is performed in one of three modes: current address read, random read, and sequential read. For reading, a device receives a device address and R/ W (= 1) after a start condition. After read data is sent, terminate a read operation by generating a high acknowledge signal (or releasing the bus without supplying an acknowledge signal) and then supplying a stop condition. (1) Current address read The internal address counter maintains the address that is next to the last accessed (read or written) word address (n). In current address read mode, data is read from address n + 1, as indicated by the address counter. In current address read mode, supplying a device address and R/ W (= 1) after a start condition, causes the device to generate a low acknowledge signal and send a data at the address indicated by the internal address counter. The address counter is incremented on the falling edge of the SCL pulse where a data at the eighth bit is sent. If the previous operation was reading data from the last address, the current address is rolled over to address 0. If the previous operation was writing data to the last address of the page, the address is rolled over to the first address of the page. The current address is maintained in an internal register so that it is lost when the power is turned off. For the first read after power-up, specify an address by performing a random read. S T A R T SDA LINE R E A D DDDDDDDD 76543210 READ DATA N O A C K Address increment S T O P DEVICE ADDRESS 1010 M S B AAA 1 210 LRA S/C BW K Figure 7 6 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU (2) Random read A random read reads data at a specified address. A dummy write is necessary to specify an address. In random read mode, supply a device address, R/ W (= 0), and a word address after a start condition. Unlike a byte or page write, where write data is supplied immediately, a dummy write only specifies a word address. Then, supply a start condition and transfer a device address and R/ W (= 1) in the same way as for a current address read, to read data from the specified address. S T A R T SDA LINE W R I T E S T A R T R E A D DDDDDDDD 76543210 A C K DATA (n) READ DATA (n) N O A C K S T O P DEVICE ADDRESS 1010 M S B WORD * ADDRESS (n) DEVICE ADDRESS 1010 M S B A AA 0 2 10 WWWWWWWW 76543210 LA SC BK AAA 1 210 L S B LRAM S / CS BW K B DUMMY WRITE *: Optional for the TC9WMB1A. Address increment Figure 8 (3) Sequential read A sequential read reads data sequentially from successive word addresses. For either current address read or random read, upon receiving a start condition, a device address and R/W (= 1), an acknowledge (low) is placed on the SDA line, followed by the data at the address pointed to by the internal address counter. When an acknowledge (low) is then received, the word address is automatically incremented so that the next data is driven out. After the last address is reached, the word address is rolled over to address 0. DEVICE ADDRESS SDA LINE R E A D 1 RA /C WK DDDDDDDD 76543210 DATA (n) READ DATA (n) A C K DDDDDDDD 76543210 DATA (n + 1) READ DATA (n + 1) A C K DDDDDDDD 76543210 DATA (n + 2) READ DATA (n + 2) A C K DDDDDDDD 76543210 DATA (n + m) READ DATA (n + m) N O A C K S T O P Address increment Address increment Address increment Address increment Figure 9 7 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU 7. Notes on Use (1) Powering up the device This device contains a power-on clear circuit, which initializes the internal circuit of the device when the power is turned on. After initialization, the address counter returns to the first address 00H and the SDA pin goes to the high-impedance state (standby state). If initialization fails, the device may malfunction. When powering up the device, observe the following precautions to assure that the clear circuit will operate normally: (a) Pull SCL and SDA "high". (b) The power rising time (tR) must be 10 ms or less. (c) After turning off the power, wait at least 100 ms (tOFF) before attempting to power up the device again. (d) The supply voltage must rise from 0 V. - (e) After turning on the power, wait at least 10 ms before attempting to send an instruction to the device. VCC VCC 0V - 0V tOFF tR 10 ms Figure 10 (2) Pulling up the SDA and SCL pins The device requires the SDA and SCL pins to be pulled up with an external resistor. The recommended pull-up resistance range is 1 k to 10 k. Noise elimination time for the SDA and SCL pins The device contains a low-pass filter for eliminating noise on the SDA and SCL pins. Its guaranteed value corresponds to the noise suppression time Ti, given in the AC characteristics table. Write operation (a) The address counter is incremented when a write instruction is received successfully. It is incremented on the falling edge of the SCL pulse where the least significant bit of data is received. (3) (4) D1 D0 Increment Figure 11 Increment Timing Diagram 8 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU (b) If a start condition is issued while the device is receiving a write instruction (device address, R/W, address, and data), this write instruction is discarded and the next instruction is accepted. (A byte write is given below as an example. This is the same as a page write.) Write instruction Start Device address R/W ACK Address ACK Data ACK Stop Address counter is not incremented during this period. Incremented. (c) If a stop condition is issued while the device is receiving a write instruction (device address, R/W, address, and data), the device enters the standby state. However, the device ignores the stop condition while sending an acknowledge signal after it receives the D0 bit. (A write operation starts.) (A byte write is given below as an example. This is the same as a page write.) Write instruction Start Device address R/W ACK Address ACK Data ACK Stop Address counter is not incremented during this period. Incremented. A write operation starts. (d) No instruction is accepted while a write operation is in progress (after a stop condition for a write instruction is received). (The device does not receive a start or stop condition during this time.) (5) Read operation (a) The address counter is incremented when a read instruction is received successfully. It is incremented on the falling edge of the SCL pulse where the least significant bit of data is driven. D1 D0 Increment Figure 12 Increment Timing Diagram (b) If a start condition is issued while the device is receiving a read instruction (device address, R/W, address, or data), this read instruction is discarded and the next instruction is accepted. (A start condition is accepted even during data transfer.) (A current address read is given below as an example. This is the same as the other read modes.) Read instruction Start Device address R/W ACK Data NACK Stop Address counter is not incremented during this period. Incremented. 9 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU (c) If a stop condition is issued while data is read (device address, R/W, address, and data), the device enters the standby state. (A stop condition is accepted even during data transfer.) (A current address read is given below as an example. This is the same as the other read modes.) Read instruction Start Device address R/W ACK Data NACK Stop Address counter is not incremented during this period. Incremented. (d) If a start condition is issued while data is read, the SDA pin changes from output to input mode and the device is ready to accept the next instruction. (6) Software reset The device cannot be reset externally because it does not incorporate a RESET pin. Instead, the device is reset by software. The software resets the device to the same state using the power-on clear circuit. The address counter returns to the first address 00H and the SDA pin goes to the high-impedance state (standby state). The software reset is invoked when a start condition is generated followed by nine SCL clock pulses (dummy cycles). While a dummy cycle is inserted, the SDA line must be pulled high. This reset operation stops an acknowledge output and data transfer. The reset is completed by generating another start condition. Issue a stop condition before starting a new transfer. Start conditions of five times or more cannot be generated from stop condition to the next stop condition. SCL Start condition 1 2 Dummy cycles 8 9 Start condition Stop condition SDA Figure 13 Software reset 10 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU Absolute Maximum Ratings (Note) (GND = 0 V) Characteristics Supply voltage Input voltage Output voltage Power dissipation Storage temperature Operating temperature Symbol VCC VIN VOUT PD Tstg Topr Rating -0.3 to 7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 Unit V V V mW C C 300 (25C,SM8) 200 (25C,US8) -55 to 125 -40 to 85 Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Operating Ranges (Note) (GND = 0 V, Topr = -40 to 85C) Characteristics Supply voltage (for reading) Supply voltage (for writing) Symbol VCC VCC Test Condition Min 1.8 2.3 0.7 x VCC 0.8 x VCC 0 0 0 0 Max 3.6 3.6 VCC Unit V V 2.3 V VCC 3.6 V High-level input voltage VIH 1.8 V VCC < 2.3 V 2.3 V VCC 3.6 V Low-level input voltage VIL 1.8 V VCC < 2.3 V Operating frequency fSCL 2.3 V VCC 3.6 V 1.8 V VCC < 2.3 V V VCC 0.3 x VCC 0.2 x VCC 400 100 V kHz Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. 11 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU Electrical Characteristics DC Characteristics (GND = 0 V, Topr = -40 to 85C) Characteristics Input current Output leakage current Low-level output voltage Quiescent supply current Supply current during read Supply current during write Symbol ILI ILO VOL ICC1 ICC2 ICC3 Test Condition 1.8 VCC < 2.3 V 2.3 VCC 3.6 V Min Unit A A Max 1 1 Min Max 1 1 IOL = 3.2 mA IOL = 1.5 mA 0.4 0.5 5 0.2* V A 5 0.3 1.5 f = 400 kHz f = 400 kHz mA mA *: f = 100 kHz AC Characteristics (GND = 0 V, Topr = -40 to 85C) Test Conditions Input rise/fall time Input/output testing voltage Output load 20 ns 0.5 x VCC 100 pF + 1 k pull-up resistor SDA CL = 100 pF VCC RL = 1 k Characteristics SCL clock frequency SCL clock low time SCL clock high time Noise suppression time SDA output delay Bus free time Start condition hold time Start condition setup time Data input hold time Data input setup time SCL, SDA input rise time SCL, SDA input fall time Stop condition setup time SDA output hold time Symbol fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH 1.8 VCC < 2.3 V 2.3 VCC 3.6 V Min 0 4.7 4.0 Max 100 Min 0 1.2 0.8 Max 400 Unit kHz s s 100 4.5 50 0.9 ns s s s s 0.1 4.7 4.0 4.7 0 300 0.1 1.2 0.6 0.6 0 200 ns ns s s s 1.0 0.3 0.3 0.3 4.7 100 0.6 50 ns 12 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU EEPROM Characteristics (GND = 0 V, 2.3 V VCC 2.7 V, Topr = -40 to 85C) Characteristics Write time Rewrite endurance Data retention time Symbol tWR NEW tRET Test Condition Min Typ. 5 Max 12 Unit ms Times Years 1 x 10 10 EEPROM Characteristics (GND = 0 V, 2.7 V < VCC 3.6 V, Topr = -40 to 85C) Characteristics Write time Rewrite endurance Data retention time Symbol tWR NEW tRET Test Condition Min Typ. 5 Max 10 Unit ms Times Years 1 x 10 10 Capacitance Characteristics (Ta = 25C) Characteristics Input capacitance Output capacitance Symbol CIN CO Test Condition VCC (V) 3.3 3.3 Typ. 4 3 Unit pF pF 13 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU AC Characteristics Timing Charts tF SCL tSU.STA SDA (Input) tAA SDA (Output) tDH tBUF tHD.STA tHD.DAT tSU.DAT tSU.STO tHIGH tLOW tR Figure 14 Bus Timing SCL SDA (Input) DO tWR Write data input Acknowledge output Stop condition Start condition Figure 15 Write Cycle Timing 14 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU Input/Output Circuits of Pins Pin Type Input/Output Circuit Remarks WP A0, A1, A2 SCL Input SDA Input/output Open-drain output 15 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU Package Dimensions Weight: 0.01 g (typ.) 16 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU Package Dimensions Weight: 0.02 g (typ.) 17 2007-10-19 TC9WMB1AFK/FU,TC9WMB2AFK/FU RESTRICTIONS ON PRODUCT USE * The information contained herein is subject to change without notice. 20070701-EN GENERAL * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer's own risk. * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. * Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 18 2007-10-19 |
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